VLSI Design For Low PDP Domino Logic

Title: Research & Implementation Requirement – Ultra Low PDP Domino Logic Design for IEEE Publication Project Objective I need an experienced VLSI Research Engineer with expertise in Cadence Virtuoso, Spectre Simulation, CMOS Circuit Design, Low-Power VLSI, and IEEE Paper Writing... (Budget: ₹600 - ₹1500 INR, Jobs: Circuit Design, Design Optimization, Electrical Engineering, Electronics, Engineering, Research and Development, Technical Writing)