FPGA Engineer Needed – Integer-Only 4-Bit EfficientNet on PYNQ-Z2

I am looking for an experienced FPGA and AI engineer to implement an integer-only low-bit CNN accelerator on a Xilinx PYNQ-Z2 FPGA platform. The project involves designing, implementing, and evaluating a hardware-accelerated deep learning inference pipeline using PyTorch and Xilinx Vivado/Vitis HLS. A detailed technical specification and project requirements will be shared with the selected freelancer. --- ## Scope of Work ### Software Development * Implement an EfficientNet-Lite or MobileNet-based CNN in PyTorch. * Prepare a floating-point baseline model. * Implement 8-bit quantization. * Develop a 4-bit integer-only quantized inference pipeline using fixed-point arithmetic and power-of-two scaling. * Evaluate model accuracy and compare different quantization configurations. ### FPGA Development * Design and implement the accelerator using Vivado/Vitis HLS (or RTL if appropriate). * Implement integer convolution, accumulation, scaling, and activation. * Integrate the accelerator on a PYNQ-Z2 (Zynq-7000) FPGA platform. * Generate synthesis and implementation reports. * Validate functionality using test data. ### Performance Evaluation Measure and compare: * Accuracy * LUT utilisation * FF utilisation * BRAM utilisation * DSP utilisation * Clock frequency * Latency * Throughput * Estimated power consumption --- ## Required Skills * FPGA Design * Xilinx Vivado * Vitis HLS * PYNQ-Z2 * Zynq-7000 * Verilog or VHDL * PyTorch * Python * Deep Learning * Computer Vision * CNN * EfficientNet or MobileNet * Fixed-point arithmetic * Quantization * Embedded AI --- ## Deliverables The selected freelancer should provide: * Complete source code * PyTorch implementation * Quantized models * Vivado/Vitis project * FPGA implementation * Bitstream (.bit) * Build instructions * Resource utilisation reports * Performance evaluation * Documentation explaining the implementation --- ## Timeline Approximately 4 weeks. Regular progress updates are expected throughout the project. --- ## Budget Fixed-price project. Milestone payments only. --- ## Preferred Experience Candidates with previous experience in FPGA-based CNN accelerators, low-bit neural networks, Xilinx platforms, and embedded AI will be preferred. Please include links to relevant GitHub repositories, published work, or previous FPGA projects. --- ## Screening Questions 1. Describe your experience with FPGA-based deep learning acceleration. 2. Have you previously used PYNQ-Z2 or other Xilinx Zynq platforms? 3. Have you worked with Vivado/Vitis HLS? 4. Have you implemented low-bit (4-bit or 8-bit) neural network quantization? 5. Please share links to similar FPGA or AI projects. 6. Briefly explain how you would approach this implementation. .