FPGA firmware: Artix-7 stepped-frequency radar back end (LVDS ADC capture, DSP, UDP streaming)

Take an existing, simulation-verified SystemVerilog code base to a working bitstream on the radar's Artix-7 XC7A100T board: timing closure, LVDS ADC alignment, Vivado FFT IP integration, Ethernet MAC, ILA-based bring-up with the hardware partner, and hand-over with a green regression. Scope of work • Existing code base (~2,000 lines, all benches passing in Icarus against a bit-exact Python model): clock/reset, SPI masters (AD9910 ×2, attenuators, AD9528, AD9268), register file, sweep sequencer, AD9268 DDR-LVDS receiver with IDELAY/test-pattern alignment, coherent averaging in the ADC domain, CDC FIFO, calibration multiply, background subtraction, window, IFFT wrapper, magnitude/TVG, packetiser, UDP/IP framing, command receiver, Vivado build script and constraints. • Your work: Vivado project and IP integration (xfft, MMCM, IDELAYCTRL, verilog-ethernet or TEMAC MAC), pin assignment from the ICD, timing constraints and closure at 100 MHz fabric / 125 MHz LVDS / 125 MHz RGMII, ILA insertion, bitstream and QSPI programming. • Verification: run the IFFT path in the Vivado simulator against the model's reference; extend the regression where you change RTL; keep the Python model and RTL bit-exact. • Bench bring-up with the hardware partner: LVDS eye/IDELAY window characterisation, ADC alignment with zero pattern errors, sweep timing on the scope (IO_UPDATE vs SYNC_CLK), 100 sweeps/s streaming to the host for 1 hour without loss, register-map freeze. • Housekeeping MCU (STM32) firmware: UART protocol to the FPGA and the host, PA interlock, temperatures, power monitor, fan control — small but safety-relevant. Deliverables • Vivado project (scripted, reproducible), bitstream and .mcs, timing and utilisation reports with all constraints met (no unconstrained paths). • Updated RTL/test benches with the regression still passing; simulation of the FFT path; documented changes to the register map (if any) agreed with the client's software team. • Bring-up report: IDELAY window plots per lane, alignment results, throughput/loss log, scope captures of sweep timing; ILA debug cores retained in a debug build. • STM32 firmware sources, build, protocol document. Required skills and experience • 5+ years Xilinx 7-series/UltraScale development in Vivado: constraints (XDC), timing closure, MMCM/PLL, IDELAY/ISERDES/IDDR source-synchronous interfaces, CDC discipline, ILA debugging on real hardware. • High-speed ADC interfaces (LVDS DDR ≥ 100 MSPS, JESD204 a plus) with calibration/alignment state machines you have brought up yourself. • Fixed-point DSP in fabric (NCO/mixers, accumulators, FFT IP, windowing) and the habit of verifying against a bit-exact reference model (Python/MATLAB). • Ethernet in fabric: RGMII PHY bring-up, MAC (verilog-ethernet, TEMAC or own), UDP framing; Wireshark-level debugging. • SystemVerilog verification with self-checking benches (Icarus/Verilator/xsim); Git workflow. • Embedded C for STM32 (HAL or bare metal), UART protocols, safety interlocks. Nice to have • Radar/SDR/ultrasound back-end experience; ADI AD9910/AD9528/AD9268 programming; Python for host-side test scripts; access to an Artix-7 dev board with LVDS FMC for pre-hardware work. Inputs provided by the client • Reference System architecture and Reference design decisions document (project plan) and the Reference component list. • Interface Control Document: per-sheet net list (nets, pins, levels, rates, routing rules) • Reference FPGA register map and packet format (register_map.md) • The Reference firmware package with README, register map, Python model and regression; the Jetson-side receiver/control software for end-to-end tests; the FPGA simulator used by the software team. • Hardware from the RF/mixed-signal partner.