SystemVerilog UVM Functional Verification

The RTL is already stable and synthesizable; my focus now is to complete functional verification using SystemVerilog within an existing UVM environment. The current testbench boots and runs smoke tests, but coverage is sitting at roughly 65 %... (Budget: ₹37500 - ₹75000 INR, Jobs: Debugging, Git, Perl, Regression Testing, Simulation, Test Automation, UNIX)