Senior Electronics Engineer-PCB Reverse engineering &Component Upgrade (Altium/KiCad)

**Job Title:** Senior Power Electronics Engineer – PCB Reverse Engineering & Component Upgrade (Altium/KiCad) **Job Description:** We are seeking an expert Power Electronics PCB Designer to reverse engineer, optimize, and upgrade an existing, functional mixed-signal power management control board for a domestic commercial rollout. The legacy system handles dual-source switching (High-Voltage DC Input and High-Voltage AC Input) routed to a heavy resistive load. The original hardware platform is stable, but the layout must be modernized, transitioned entirely to globally available Western components (DigiKey/Newark BOM), and optimized for heavy thermal and low-resistance loads. ### Core Project Requirements: 1. **Schematic Capture & PCB Re-Layout:** Translate high-resolution layer-by-layer optical/X-ray reference images of a legacy PCBA into fully editable, production-ready digital design files (Altium Designer preferred). 2. **Western BOM Sourcing:** Cross-reference and replace all localized integrated circuits (ICs), microcontrollers, and logic chips with active, heavily stocked Western brand equivalents (Texas Instruments, STMicroelectronics, onsemi, Micron, etc.). 3. **Heavy Power Handling Upgrades:** Optimize power routing layers to handle a continuous **High-Voltage AC input path** and a continuous **High-Voltage DC input path (up to 250V DC / max 20 Amps continuous)**. ### Strict Technical Design Constraints: * **Copper Weight:** Board power layers must be designed specifically for **3 oz. copper thickness** to manage heavy continuous current cycles. * **Standards Compliance:** Trace routing, clearance, and creepage spacing must explicitly adhere to **IPC-2152** (current-carrying capacity) and **IPC-2221** safety insulation standards to prepare the unit for domestic UL/ETL compliance. * **Component Specification:** For the DC switching stage, utilize an array of **3 to 4 discrete N-Channel Power MOSFETs rated for exactly 50-Amps and a minimum of 400V** in a standard package (e.g., TO-247) with an ultra-low Rds(on). Position these transistors in a neat row along the edge of the board to easily mate with a common, top-mounted aluminum finned heatsink block. * **Safety Isolation:** Implement heavy galvanic isolation and design a strict physical, hardware-level "Break-Before-Make" interlock routing matrix using high-current, board-mounted mechanical power relays rated for 40A–50A. * **Microcontroller Platform:** Transition the digital logic brain to a modern, highly available 32-bit architecture (such as an **STMicroelectronics STM32** or **Microchip PIC** microcontroller). * **Future Expansion Footprint (DNP Block):** Please design the master PCB layout to fully include the circuit paths and physical footprints for a standard **Espressif ESP32-S3-WROOM-1 module**. However, designate this section as a **"Do Not Populate" (DNP)** block in the initial Phase 1 Bill of Materials. The core board routing must function perfectly with this module physically absent from the circuit for our initial launch run. ### To Apply, You Must Proactively Provide: * Examples of previous PCB layouts you have completed that handle **greater than 15 Amps of continuous power**. * A brief confirmation that you understand how to design layouts matching IPC-2152 standards for heavy copper boards.