Senior Design Verification Mentor

Budget: - / ⭐ (0)

Debugging, Simulation, Software Development

I am a junior design-verification engineer working on projects that rely heavily on UVM and SystemVerilog. The scope of my day-to-day work shifts—from setting up testbenches and drafting verification plans... (Budget: ₹600 - ₹1500 INR, Jobs: Debugging, Simulation, Software Development)

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